In the processing of a substrate, e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. During substrate processing, the substrate is divided into a plurality of dies, or rectangular areas. Each of the plurality of dies will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (or etched) and deposited. Control of the transistor gate critical dimension (CD) on the order of a few nanometers is a top priority, as each nanometer deviation from the target gate length may translate directly into the operational speed and/or operability of these devices.
Typically, a substrate is coated with a thin film of hardened emulsion (such as a photoresist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing parts of the underlying layer to become exposed. The substrate is then placed on a substrate support structure in a plasma processing chamber. An appropriate set of plasma gases is then introduced into the chamber and a plasma is generated to etch exposed areas of the substrate.
During an etch process, etch byproducts, for example polymers composed of Carbon (C), Oxygen (O), Nitrogen (N), Fluorine (F), etc., are often formed on the top and the bottom surfaces near a substrate edge (or bevel edge). Etch plasma density is normally lower near the edge of the substrate, which results in accumulation of polymer byproducts on the top and on the bottom surfaces of the substrate bevel edge. Typically, there are no dies present near the edge of the substrate, for example between about 5 mm to about 15 mm from the substrate edge. However, as successive byproduct polymer layers are deposited on the top and bottom surfaces of the bevel edge as a result of several different etch processes, organic bonds that are normally strong and adhesive will eventually weaken during subsequent processing steps. The polymer layers formed near the top and bottom surfaces of a substrate edge would then peel or flake off, often onto another substrate during post treatment, such as wet cleaning of the substrate surface, potentially affecting device yield.
Ultrafine feature sizes and high performance requirements have necessitated the integration of low-k dielectrics on semiconductor wafers that are mechanically weaker than previous generation materials. The inherently weaker nature of the low-k dielectric material can pose significant challenges to downstream electronic-packaging processes and materials.
Low-k materials are, by definition, those semiconductor-grade insulating materials that have a dielectric constant (“k”) lower than 2.9. In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low-k to reduce the capacitive coupling between adjacent metal lines. Low-k dielectric, carbon, or fluorine-doped films are being integrated into back-end-of-line (BEOL) stacks to improve device performance and allow for device scaling.
However, low-k materials are porous, which introduces a host of process integration and materials compatibility difficulties. The balancing act between maintaining the film's integrity and integrating it properly and performing the necessary stripping, cleaning, and conditioning gets increasingly precarious. Patterning processes (etching, stripping, and cleaning) can also have a drastic impact on the integrity of the porous low-k. Current cleaning plasma gases used are O2 and CF4 or N2 and CF4, which results in the migration of nitrogen, oxygen, or fluorine radicals into the substrate. The migration causes the k value to increase, which changes the composition and degrades the materials.
Thus, low-k damage results in degraded device performance, reduced reliability, lost yield, and other related problems.